1. Field of the Invention
The present invention relates to a technology for analyzing a clock-delay in a circuit such as a large-scale integrated circuit (LSI).
2. Description of the Related Art
In recent years, influence of a statistical factor such as a process fluctuation on very-large-scale integrated circuit (VLSI) manufacturing becomes large due to fineness of a process. To manufacture circuits having a performance required in VLSI design with an excellent yield, it is necessary to estimates the influence in advance. In the conventional art, therefore, estimation of a clock-delay value in an object circuit is performed by a so-called statistical approach.
The statistical approach will be explained briefly with reference to FIG. 5. A difference S2 between a statistical minimum delay value “d” obtained from a delay distribution Pck of clock path in an object circuit and a statistical maximum delay value “c” obtained from a delay distribution Pda of data path is a clock-delay value in the statistical approach. As a related conventional approach, there is an approach disclosed in Japanese Patent Application Laid-Open No. 07-182381. In the approach disclosed in the above literature, a delay time analysis considering fluctuation in mutual delay between the data path and the clock path is performed.
In the conventional approach, however, there is such a problem that it is difficult to handle the statistical factor accurately. For example, when the statistical factor is handled by a conventional static delay analysis (STA), the clock-delay value is estimated based upon the worst value in the factor, namely, a difference between the statistical minimum delay value of data path and the statistical maximum delay value of clock path, so that there is such a problem that only a considerably pessimistic result can be obtained.
Therefore, there is such a problem that such a possibility occurs that a design margin cannot be satisfied so that a circuit cannot be designed. Particularly, when the statistical approach is employed, since a clock-delay value based upon the difference between the statistical minimum delay value of data path and the statistical maximum delay value of clock path is stochastically fluctuated, which results in an unstable clock-delay value and causes quality reduction in static delay analysis.